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The timing of the AD9364 output data is unstable or incorrect.

Question asked by Hugh on Jul 23, 2018
Latest reply on Jul 25, 2018 by Hugh

The timing of the AD9364 output data is unstable or incorrect.

Register configuration is as follows:

 

//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
SPIWrite 010,C8 // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
SPIWrite 011,00 // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
SPIWrite 012,02 // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
SPIWrite 006,0F // PPORT Rx Delay (adjusts Tco Dataclk->Data)
SPIWrite 007,00 // PPORT TX Delay (adjusts setup/hold FBCLK->Data)

 

Chipscope capture wave:

Can you help me with your answer? Thank you.

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