AnsweredAssumed Answered

Clock Routing

Question asked by NNEU on Jul 23, 2018
Latest reply on Aug 8, 2018 by joe42

Hi !


I recently started designing an ADAU1466 based DSP board. After first considering the standard AD1938 as codec, i quickly diverted to separate ADC and DACs (Cirrus Logic in this case).


Having respected every single design rule suggested by Analog Devices (and Cirrus Logic respectively), i feel quite confident about my design.

However, there is one question or "audiophile driven worry" that i would like to seek guidance for; the master clock trace (or CLKOUT trace; the DSP is master).


1. Question: Fanout buffer 

Is a fanout buffer necessary for the CLKOUT trace ? The ADAUs data sheet mentions that it is able to drive multiple ICs  but is rather vague on the implications.

On my board, all three ICs that need to be driven are within a 1,5 inch radius from the ADAU, so im wondering if the buffer will really provide any benefit or possibly even make things worse. 

If a buffer is recommended, i would be highly appreciative of a particular suggestion. 


2. Question: routing

I've read some papers on routing of high speed traces; clock trace being sandwiched in between two ground planes,  surrounded by via connecting the two,  as few changes in layers as possible, etc.

Those seem to be difficult to incorporate in my design. I have planned a six layer PCB with the following stackup:





-DVDD (Plane only covering the needed area underneath the DSP and according V-reg)



The suggested routing method would therefore cause planes to be split. 


On the other hand, the EVAL-ADAU1466 board seems to take a more liberal approach routing the CLKOUT line; altering layers five times before reaching the AD1938. 


Given that the fanout buffer is not needed, how should the Clock line be routed ? On which layer ? Should i route the trace to every IC separately, going out from the ADAUs CLKOUT pin, or should i place all ICs on a single trace carrying  the signal ?


Thanks in advance !