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Codec ad74111 interface

Question asked by pietrodcs on Jan 6, 2012
Latest reply on Jan 23, 2012 by pietrodcs

Good morning.

Happy new year for all of YOU.

 

I am fighting to have the codec AD74111 to work. I have prepared something like the AD7311 which

has been working successfully before. Actually the setting for the sport are identical.

I have verified on the scope the signals for the DIN of the codec and it is working.

What I do is the same I read on the document EVAL-AD74111EB for the 16-BIT DATA MODE, 16-BIT DATA, MASTER MODE.

I send the registers in the same order. I send the register A four times with a zero in between ( I don t know why it is necessary) ,

the last register is D.

I tried to send two times each register, I mean two times A, two times B ecc.... just to verify if there is a question of synch between control and

DAC data, but it is the same.

I attach and dump the code for the initialization

 

/*   
    Here it is for sending the list of config registers
    The sport is left disabled
    The Sport should be reinit for serving the comms
*/
// #pragma section("FLASH_code")
static void Sport_Config_Init( void ) {
    // This is not here requiring the RX side init
    // The SPORT will be : late frame synch, active high, ext clk, MSB first, Norm op, ext frame synch, require frame synch
    // secondary disable word length 16
    *pSPORT_TCR1 = TFSR;
    *pSPORT_TCR2 = 0x0F;
    *pSPORT_STAT = TXHRE;
    *pSPORT_STAT = TOVF;
    *pSPORT_STAT = TUVF;
    *pSPORT_STAT = RUVF;
    *pSPORT_STAT = ROVF;
}

 

// #pragma section("FLASH_code")
static void SportTxEnable( void ) {
    *pSPORT_TCR1 |= TSPEN;
}

 

// #pragma section( "FLASH_code" )
int Ad74111_Config_Init( void ) {

 

    // unsigned short ctrl_regs[8];
    unsigned short status = 0;
    static volatile int count = 0;
    TRegA RegA;    
    TRegB RegB;    
    TRegC RegC;    
    TRegD RegD;    
    TRegE RegE;    
    // TRegF RegF;    
    TRegG RegG;    
   
    RegA.rw = Erw_write;
    RegA.Addr = REGA_ADDR;
    RegA.Res = 0;
    RegA.Reserv = 0;
    RegA.ADCInpAmp = EOn;
    RegA.ADCOn = EOn;
    RegA.DACOn = EOn;
    RegA.RefOn = EOn;
    RegA.RefAmpOn = EOn;
    RegA.Res2 = 0;

 

    RegB.rw = Erw_write;
    RegB.Addr = REGB_ADDR;
    RegB.Res = 0;
    RegB.Reserv    = 0;
    RegB.clk3_div = EMclk3_div1;
    RegB.clk2_div = EMclk2_div3;
    RegB.clk1_div = EMclk1_div1;

 

    RegC.rw = Erw_write;
    RegC.Addr = REGC_ADDR;
    RegC.Res = 0;
    RegC.Reserv    = 0;
    RegC.ADDAWidth = EADDA_Len16;
    RegC.LowDelay = EEnable;
    RegC.DACDeEnph = EDACDeEnph_None;
    RegC.ADCHPass = EEnable;

 

    RegD.rw = Erw_write;
    RegD.Addr = REGD_ADDR;
    RegD.Res = 0;
    RegD.MFrame    = EMFrame_Normal;
    RegD.Reserv = 0;
    RegD.DMode = EDMode_Data;
    RegD.DspMode = EDspMode_16;
    RegD.FastDClk = EFastDClk_256;
    RegD.MSMode    = EMSMode_Master;

 

    RegE.rw = Erw_write;
    RegE.Addr = REGE_ADDR;
    RegE.Res = 0;
    RegE.Reserv    = 0;
    RegE.ADCL_PkEn = EDisable;
    RegE.ADCGain = EADCGain_9dB;
    RegE.ADCMute = EDisable;
    RegE.DACMute = EDisable;
    /*
    RegF.rw = Erw_write;
    RegF.Addr = REGF_ADDR;
    RegF.Res = 0;
    RegF.Reserv    = 0;
    RegF.InpPeak = 0;
    */
    RegG.rw = Erw_write;
    RegG.Addr = REGG_ADDR;
    RegG.Res = 0;
    RegG.DACVol = 0;

 

    Ad74111_IO_Init();
    // Sport_Config_Init();
    for (count = 0; count < 100000; count++);
    RESET_LOW;
   
    RESET_HI; // tRH  5MCLKS
    for (count = 0; count < 100000; count++);

 

    Sport_Config_Init();
    ssync();
    /* SPORT Tx Register is a 8 x 16 FIFO, all the data can be put to
     * FIFO before enable SPORT to transfer the data
     */
    *pSPORT_TX16 = RegA.W;
    *pSPORT_TX16 = 0;
    *pSPORT_TX16 = RegA.W;
    *pSPORT_TX16 = 0;
    *pSPORT_TX16 = RegA.W;
    *pSPORT_TX16 = 0;
    *pSPORT_TX16 = RegA.W;
    *pSPORT_TX16 = 0;
    /*
    *pSPORT_TX16 = RegB.W;
    *pSPORT_TX16 = RegB.W;
    *pSPORT_TX16 = RegC.W;
    *pSPORT_TX16 = RegC.W;
    *pSPORT_TX16 = RegE.W;
    *pSPORT_TX16 = RegE.W;
    */
   
    status = *pSPORT_STAT;

 

    ssync();
    SportTxEnable();
    ssync();
    count = 0;
    status = *pSPORT_STAT;

 

    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }

 

    *pSPORT_TX16 = RegB.W;
    status = *pSPORT_STAT;
   
    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;
   
    *pSPORT_TX16 = 0;
    status = *pSPORT_STAT;
   
    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;

 

    *pSPORT_TX16 = RegC.W;
    status = *pSPORT_STAT;
   
    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;

 

    *pSPORT_TX16 = 0;
    status = *pSPORT_STAT;
   
    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;
           
    *pSPORT_TX16 = RegE.W;
    status = *pSPORT_STAT;
   
    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;
   
    *pSPORT_TX16 = 0;
    status = *pSPORT_STAT;
   
    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;
   
    *pSPORT_TX16 = RegG.W;
    status = *pSPORT_STAT;
   
    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;

 

    *pSPORT_TX16 = 0;
    status = *pSPORT_STAT;

 

    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;
   
   
    *pSPORT_TX16 = RegD.W;
    status = *pSPORT_STAT;

 

    while ( (status & TXF) && (count++ < TIMEOUT) ) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        status = *pSPORT_STAT;
        ssync();
    }
    if ( count >= TIMEOUT )    goto LExit;
   
    *pSPORT_TX16 = 0;

 

    /* When TUVF is set, the data is already send out */
    status = *pSPORT_STAT;
    while (!(status & TUVF) && count++ < TIMEOUT) {
        int cnt;
        for (cnt = 0; cnt < 1000; cnt++);
        // udelay(1);
        status = *pSPORT_STAT;
        ssync();
    }
LExit:
    *pSPORT_STAT = TUVF;
    *pSPORT_STAT = TXF;
    SportTxDisable();
    // bfin_write_SPORT_TCR1(bfin_read_SPORT_TCR1() & ~TSPEN);
    ssync();
    // local_irq_enable();

 

    if (count >= TIMEOUT) {
        return -1;
    }
    return 0;

 

}

 

I hope You find the arcan

 

Thank You

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