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Is there any way to pause the AD9680 chip from sampling(only using the configuration on AD9680 chip, not FPGA).

Question asked by chwe3468 on Jul 19, 2018
Latest reply on Jul 19, 2018 by UmeshJ

Hi,

 

I wonder if there is any way to pause the AD9680 chip from sampling(only using the configuration on AD9680 chip, not FPGA).

I check the AD9680 documentation, I haven't found anything talks about how to pause sampling. I also looked at the following discussion, but unfortunately, it seems like the external trigger used in this pdf is implemented in FPGA. 

https://ez.analog.com/docs/DOC-17546-can-i-use-an-external-trigger-to-capture-data-from-ads7-v2ebz

I think the FPGA is buffering sample data from ADC (while ADC is always sampling non-stop). And a trigger event will trigger FPGA to find a certain amount of samples from the buffer. However, this implementation requires some memory resources on FPGA and I also need to take a lot of transmission delay into account, since the trigger is sync with ADC but not FPGA. I either need to shift the trigger signal or tell FPGA to take data from the data buffer at a shifted time.

My guess will be: there is no way to do this since AD9680 has a pipelined architecture, but I just want to confirm this. Or maybe there is another chip that has this feature? Do anyone have an idea?

 

Thanks!

 

Best wishes,

Chutao

 

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