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Some problem in axi_ad9361_rx_pnmon

Question asked by xiaozhupeiqi on Jul 19, 2018
Latest reply on Jul 22, 2018 by xiaozhupeiqi

I have encountered some problems in my AD9361+FPGA program.

My hardware is KCU105+FMCCOMS3. I customized my own AD9361 project based on the reference hardware HDL design. And configuration command from no-os.

I use xdma IP core to replace Mircoblaze in reference HDL design. I use xdma IP core to control AXI-QUAD-SPI IP core and AXI-ad9361 IP core.

When the Data_clk is 61.44MHz, our design can pass PN check. But our PN check error when Data_clk is 122.88MHz. 

We try to use offical PN check algorithm, but RX  tuning failed.(We are currently only concerned with the receiving )


After analyzing the debug signal, I found two problems. The first is shown as below.


The data is spliced incorrectly in the axi_ad9361_rx_pnmon module. After ‘tadc_pn_data_in <= {adc_pn0_data_in[7:0], adc_pn0_data_in};  ‘’0 becomes 1.


always @(posedge adc_clk) begin
if (adc_pnseq_sel == 4'h9) begin
adc_pn_valid_in <= adc_pn1_valid_in;
adc_pn_data_in <= adc_pn1_data_in;
adc_pn_data_pn <= adc_pn1_data_pn;
end else begin
adc_pn_valid_in <= adc_pn0_valid_in; //sel==0
adc_pn_data_in <= {adc_pn0_data_in[7:0], adc_pn0_data_in};
adc_pn_data_pn <= {adc_pn0_data_pn[7:0], adc_pn0_data_pn};


And the second problem is adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0; The 'dead' appear.

always @(posedge adc_clk) begin
adc_pn0_valid <= adc_valid;
adc_pn0_data <= (adc_pn0_iq_match_s == 1'b0) ? 16'hdead : adc_pn0_data_s;
adc_pn0_valid_in <= adc_pn0_valid;
if (adc_pn0_valid == 1'b1) begin
adc_pn0_data_in <= adc_pn0_data;
adc_pn0_data_pn <= pn0fn(adc_pn0_data_pn_s);


Can I fix these two errors by adjusting the IDELAY in the FPGA program?