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AD9172 Clock Question

Question asked by AxelYs on Jul 18, 2018
Latest reply on Aug 3, 2018 by landsman

Hi everyone,

 

Currently, I am evaluating the performance of AD9172 with ADS7-V2. I go through the user guide (AD917x-FMC-EBZ Evaluation Board User Guide [Analog Devices Wiki] ) and AD9172 schematic diagram. However, I am quite confused about the direct clock option described in the user guide.

Q1:

In the user guide, to direct clock AD9172, we need to rotate C36 and C38 to instead be populated on C34 and C35. Connect a high-performance clock with >=12dBm output level to J34 for the direct clock option. In addition to this, a second low phase noise, high frequency clock source (3.84MHz , 7.68MHz, 15.36MHz, 30.72MHz, 61.44MHz, 122.88MHz, 245.76MHz and 491.52MHz) with 0 dBm output level that is the reference clock of the HMC7044 should be connected to the SMA connector J41. However, after studying the schematic diagram, I am quite confused why we need the second clock source connected to J41. Here is the circuit diagram:

Circuit diagram

When we rotate C36 and C38 to instead be populated on C34 and C35, we disable the HMC7044_CLKIN_N and HMC7044_CLK_P. The signal fed into J34 will go directly to AD9172 (CLKIN_P and CLK_N). In this case, why is it still necessary to connect a second clock source to J41? I think if we change the position of C36 and C38, we basically disable the HMC7044. Am I correct?

Q2: 

In addition to this, I have another question about HMC7044 and AD9172. For our application, we need to synchronization AD9172 with other devices. Therefore, it is required to make sure all clocks are from one common high quality oscillator. We are trying to connect our high quality 10MHz oscillator to J41 as HMC7044 reference clock. And the output of HMC7044 will go to AD9172 via HMC7044_CLK_N and HMC7044_CLK_P (through CLKOUT2 of HMC7044). In this case, how can we configure ACE? Here is a screenshot of ACE:

For the HMC7044 PLL1 Ref Clock source configuration, I set HMC7044 PLL1 Ref Clock Source to 'User Input (J41)'. For HMC7044 PLL1 Ref Clock, I set to 'Other frequency', since 10MHz is not in the list. Am I correct?

How about the AD917x setting? My understanding is that, if I set AD917x PLL Ref Clock to 100MHz (for example), the HMC7044 will generate 100MHz from 10MHz input reference clock and output this 100MHz to AD9172. Is it the way how it works? If not, please correct me!

 

Regards

Zichuan Zhou

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