I´m designing a circuit based on ADI´s AD9956 like the typical aplication circuit showed on Figure 24. LO and Baseband Modulation Generation" AD9956 datasheet, page 16.
On page 12 says:
PIN Mnemonic Description
20 I/O_UPDATE This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT.
On that typical application the SYNC_CLK signal is the output of R divider, and the PLLref signal is provided by a crystal. But, i need that AD9956 recognice the I/O_Update signal to:
- Enable cristal oscillator
- Configure CML driver
- Configure R diveder
-Configure N and M dividers.
- Others configuratons.
How is it possible if I dont have the SYNC_CLK signal when I start AD9956?
For example, on AD9912 from ADI too the I/O_Update signal is completely asynchronous.
Can some one clear my doubt?