I tried to add the DMA IP Core into the official project,when synthesis,some errors and critical warnings appeared as shown below.How to solve it?
Have you gone through : Building HDL [Analog Devices Wiki] ?
There was no error when I followed the reference HDL design,but when I added a XDMA IP Core to the project,these errors appeared.Is it not allowed to add user IP to the official project?
Not sure what official project you are referring to, can you tell me more about it ? The IP can be used in any project.
Can you describe the steps you are performing to add the IP ?
The project which I referring is the 2018r1.
I added the IP into this project in the Block Design of Xilinx Vivado 2016.4,then,when I operated 'generate output products',Vivado sent lots of errors and critical warnings.
2018_r1 is a release branch for us, not a project. You are refering to the branch ? Which project from that branch ?
2018_r1 branch was tested with Vivado 2017.4. Can you use that version of Vivado ?
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