I have a question LTC2321-16.
Is it okay if we can change the 220pF in front of the ADC to 10pF?
This capacitor serves as a charge reservoir to absorb the sampling transients from the ADC. There is generally a balance between the peak value of the transient and the time it takes for the transient to settle out. You can reduce the value of this capacitor quite a bit before you encounter settling time issues. Even a 10pF capacitor should settle to within 16 bit accuracy after about 8nsec.
The reason this capacitor is 200pF is to reduce the noise reaching the ADC input. It is part of an RC filter, which serves as an anti-aliasing lowpass. As it stands, the 3dB bandwidth of the filter is near 14.5MHz. Reducing the capacitor to 10pF will increase this bandwidth to several hundred MHz. That will reduce the SNR, as well as allow higher frequency signals to alias into the sampled output.
Let me ask why you would like to reduce this capacitance?
Thank you for your answer.
Unfortunately we don't have a spec we can guarantee SCK to CLKOUT max delay. If you are using the SCK signal as it leaves the ASIC, you will also have to account for the transit time from ASIC to ADC.
The best way is to use the CLKOUT signal to time the data entering the ASIC.
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