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AD9371 Profile Generator Device Clock Limitations

Question asked by fpga-dev2 on Jul 17, 2018
Latest reply on Jul 18, 2018 by larsc



I'm trying to generate a profile using the AD9371 Filter Wizard v1.10 with an RX sample rate of 126 MHz, ORX and TX sample rates of 252 MHz, and a device clock of 126 MHz using a modified VCXO frequency of 100 MHz and RefClk at 10 MHz. 


According to this link AD9371 Evaluation Board  VCXO selection  I should be able to generate this profile with values:

M1: 3

N2: 38

R1: 3

chDIV: 10


This gives a VCO of 3800 MHz (within the limits of 3450 to 4025 MHz) and a device clock of 126 MHz.


This all works fine. However, if I then select "Write AD9528 Settings To File", set VCXO at 100 MHz and RefClkA at 10 MHz, I can no longer select a device clock of 126 MHz! My nearest options are 120 MHz or 140 MHz. 


In the MATLAB source files, the function AD9528_Rates() does not look to include an option for the 5-bit divider R1. This looks to limit the value of N2 unnecessarily. Similarly, this functions limits the output channel divider to the range of 3-50, even though the above link states the allowable range is in the range of 1-256. 


Is there something I'm missing here?