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Issues building the ADRV9009/ZCU102 HDL Project

Question asked by ngcstw on Jul 17, 2018
Latest reply on Jul 18, 2018 by mhennerich

There were two issues. For both I found workarounds. (Building with Vivado 2018.2.)

 

Issue 1: Project build errors.

Excerpt from build log:
  ...
  ## source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
  ...
  ### ad_connect  sys_ps8/emio_spi0_ss_i_n VCC
  ...

  ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Width(CONST_WIDTH)' for "Const Value is out of range -0:1 allowed by width"
  . BD Cell 'sys_ps8_emio_spi0_ss_i_n_VCC'
  ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Const Val(CONST_VAL)' for Const Value is out of range -0:1 allowed by width
  . BD Cell 'sys_ps8_emio_spi0_ss_i_n_VCC'
 
Workaround 1: In zcu102_system_bd.tcl commented out offending lines 100 and 113 :
  100 #ad_connect  sys_ps8/emio_spi0_ss_i_n VCC
  113 #ad_connect  sys_ps8/emio_spi1_ss_i_n VCC

 

Issue 2: In synthesis got two errors (subsequently)


  ERROR: [Synth 8-1766] cannot open include file inc_id.h [/data/nas/md12-fs17/md12-fs17/ES/ECAD/stargazer_fpga/users/walsh/RS/debug/hdl-master/projects/adrv9009/zcu102/adrv9009_zcu102.srcs/sources_1/bd/system/ipshared/6002/address_generator.v:74]
  ERROR: [Synth 8-1766] cannot open include file resp.h [/data/nas/md12-fs17/md12-fs17/ES/ECAD/stargazer_fpga/users/walsh/RS/debug/hdl-master/projects/adrv9009/zcu102/adrv9009_zcu102.srcs/sources_1/bd/system/ipshared/6002/response_generator.v:58]

 

Workaround 2: Copied the missing files from other folders. Completed synthesis/implementation/bit file generation in the GUI.

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