Hello. I am currently using the Qsys ADRV9371 reference design for the 2017 R1 branch. The FPGA reference design makes use valid lines for each 2x2 I & Q channel. If we examine the axi_ad9371 IP core with the adc_ch_0/1/2/3
I am using the libIIO API calls (iio_buffer_push and iio_buffer_refill) to read and write data as well as specifying frame-sizes. I would then set the buffer size by using the iio_device_create_buffer( ) call.
I would like to understand the IIO software behavior of toggling these valid lines in the PL. I am inserting my own receiver IP that will fit between the axi_ad9371 IP and the axi_ad9371_rx_cpack IP block.
In this IP contained on the Rx path, I am connecting all the valid lines from the same source within my design to control how much data gets sent back to the Cpack/DMA engine. This works as expected. However, what is the effect of toggling each of the four valid lines independently? Does the Cpack/DMA only accept samples when all four valid lines are high or is it capable of waiting on each I/Q channel separately until the desired number of samples of the specified frame-size fills the buffer specified by iio_device_create_buffer() ? What impact does this have on iio_buffer_refill( ) ?
Also, will there ever be instances where some of the valid lines coming from the axi_ad9371 for I / Q be low while others are high or are they always synchronized?