We have developed our own prototype boards with AD9361. To control of the AD9361 chip we are using a small Xilinx FPGA, but no DDR3 Memory. The Demo Firmware (FW) and Software(SW) from ADI is designed for different FPGA Evalboards, that all have DDR on them.
Our application does not need as many setup options, as provided by the demo-FW/SW. What we need is a smaller firmware with reduced functionality. I need some assistance with the following points:
- Can the Memory Interface Generator (MIG) be removed from the FPGA design just like that, i.e. is the DDR only used for saving RX data (our application won’t need that)? Or will there be performance issues when running the no-OS software from LUTRAM/BRAM found in the FPGA?
- What must be done for a clean MIG removal?
- Thank you.