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AD9144 multiple DACs and deterministic latency

Question asked by maryg on Jul 16, 2018
Latest reply on Jul 18, 2018 by deljones

Hi,

 

two AD9144 are mounted on the same custom board. They both need to have the same repeatable latency. This feature is described in section "Theory of operation" on pag 21 of AD9144 rev B datasheet:

 

 

We would like to review with you the link delay setup procedure in the "Without Known Delays" case.

 

1)  we follow the procedure described in pag 32 of AD9144 rev B datasheet:

 

After point 2, the link is up.


During point 3 we do as follows:

 

AD9144 #0:
write addr 0x301 val 0x01
write addr 0x03A val 0x01
write addr 0x03A val 0x81
write addr 0x03A val 0xC1

 

AD9144 #1:
write addr 0x301 val 0x01
write addr 0x03A val 0x01
write addr 0x03A val 0x81
write addr 0x03A val 0xC1

 

SEND SYSREF to both DAC, then:

 

AD9144 #0:
write addr 0x300 val 0x01

 

AD9144 #1:
write addr 0x300 val 0x01

 

While performing this test, what values should be written in reg 0x304 to 0x306?

 

 

The example found at section "Link Delay Setup Example, Without Known Delay", pag 46 of AD9144 rev B datasheet says that it should be: LMFCDel = 0. What about LMFCVar? Should it be LMFCVar = 0xA (maximum value allowed)?

 

2) again, on pag 32 of AD9144 rev B datasheet it is said that:

 

If the value read in reg 0x303 over 20 start up cycles is between 0 and 2, do we exchange 0 with 8, 1 with 9 and 2 with 10 or do we keep them as is?

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