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PPI Loopback (Tx&Rx) on same core on BF561

Question asked by clim on Jan 4, 2012
Latest reply on Jan 6, 2012 by PrasanthR



I am trying to do a simple loopback from the BF561 to FPGA and back. I have built standalone projects for just Tx and Rx via PPI0 and PPI1 respectively and they work just fine. The problem I encountered when I try to stitch the two projects together in CoreA into a loopback project is the Tx data somehow becomes out of order and jumbled. I have attached a picture showing this. On the left, in RED is the data from the DSP being sent through PPI1. You may notice that everything looks fine up until #73 where it goes back to #70 and the sequence becomes jumbled. On the right, in the console the first 31 'printfs' (note #0 is hidden above the screen) display the contents of the 3 Tx buffer. The buffers contain sequenial numbers starting at 2 and ending at 97. The buffers were initiliazed using the following code:


void init_buffers(void) {
    unsigned int i;
    for (i=0; i<frame; i++) {

        buffer0_out[i] = i+2;
        buffer1_out[i] = frame+i+2;
        buffer2_out[i] = 2*frame+i+2;


It would appear to me that receiving data via PPI0 works fine, the problem is sending. I have tried disabling PPI0 and just running PPI1 and the data does transfer correctly. As far as I can see, the problem occurs when I try to run both PPI0 and PPI1 at the same time.


Has anyone tried to do a loopback where both PPI buses are on the same core?