I made an FPGA program based on the reference HDL design.The axi_ad9361_0 module in the figure is the same as the HDL reference design. I just deleted some Input and output signals.And I use the xdma IP core to send commands, which are modified by the no-os.
I used the algorithm of the reference design for digital interface tuning, but the tuning failed.
I tried to change the value of the 0x006 register, but the waveform has a glitch in the BIST tone mode.
Does this indicate that the reference digital interface calibration method is not suitable for my design? Do I need to adjust the idelay module?