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Adjust the timing of the AD9361 digital interface

Question asked by S.Pang on Jul 15, 2018
Latest reply on Jul 16, 2018 by CsomI

I made an FPGA program based on the reference HDL design.My hardware platform is KC705+FMCOMMS3. The axi_ad9361_0 module in the figure is the same as the HDL reference design. I just deleted some Input and output signals.And I use the xdma IP core to send commands, which are modified by the no-os.

I used the algorithm of the reference design for digital interface tuning, but the tuning failed.

I tried to change the value of the 0x006 register, but the waveform has a glitch in the BIST tone mode.

Does this indicate that the reference digital interface calibration method is not suitable for my design? Do I need to adjust the idelay module?

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