I have some questions about AD9361 Rx Clock and Data Delay register(0x006).
Follow the instructions in UG671.
Is the effect of setting the register to 00010001 the same as setting to 00100010 ?
Is RX CLOCK the same as rsample clk in the figure?
Is the Data Delay the same as Rx Data in the figure?
I made an FPGA program based on the reference HDL design.My hardware platform is KC705+FMCOMMS3. The axi_ad9361_0 module in the figure is the same as the HDL reference design. I just deleted some Input and output signals.And I use the xdma IP core to send commands, which are modified by the no-os.
When I set Rsample clk to 1.92MHz, I can adjust to BIST tone mode and observe a sine wave. But when I set the receive clock to 3.84MHz, adjust to BIST tone mode, the observed sine wave has glitch, I tried to change the 0x006 register from 00 to 0F, but the glitch still exists. Does it mean that only changing the 0x006 register is not enough, i need to change the idelay in axi_ad9361 mode?
The glitch is shown below.