I'm using ad9364 and ZedBoard
since the hdl labelled "fmcomms2" can be used for all different fmcomms2/3/4 boards .. I want to modify the hdl to use only one Rx/Tx for ad9364 .. fmcomms2 has 4 channels (i0,q0,i1,q1) ...
what things I should change?
for example, Do I need to change MODE_1R1T in AXI_AD9361 component.
configure upack and cpack utility to delete the second channel!
what about clocking! is it going to give me more data rate instead of 61.44! or it is limited by the chip and interface type (cmos - lvds) as I understand!
The reason I'm doing that is to reduce fpga resources!