AnsweredAssumed Answered

sys clk on eval board

Question asked by avinash on Jan 3, 2012
Latest reply on Feb 6, 2012 by DSB


the evaluation board for the ad9912 specifies the amplitude setting for the sys clk as +3dbm, .

what is the impedance seen through the sys clk terminal on the evaluation board.

what is the input resistance on the board ,(not the DDS)

also on application of the signal there seems to be a slight DC offset for the signal reaching the DDS finally,

and hence the negative side of my sine wave do not have a 316 mV value.

Is there something that i missed out.


Also if iam taking the sine wave from a 50 ohm terminated generator,i think eval board offers lesser resistance ,

hence shouldn't i use a buffer. wouldn't this give the result.


thanks in advance