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AD9517 unrecognized CHIP_ID and cf-ad9361-dds/lpc not visible

Question asked by tgm on Jul 12, 2018
Latest reply on Jul 17, 2018 by travisfcollins

Hi,

I work with ADRC1CRR-FMC (previously AES-PZSRDCC-FMC-G) and I try to run the custom bitstream/FPGA with custom device tree on a custom Linux O/S. Goodluck me. :)

This is the kernel:

root@xxx:~# uname -a
Linux xxx 4.6.0-xilinx-ga8f23b8100e2-dirty #16 SMP PREEMPT Tue Jul 10 17:37:44 CEST 2018 armv7l GNU/Linux

It is dirty because I have uncommented #define DEBUG in drivers/iio/adc/ad9361.c. So not a really big deal.

Reference design:
hdl/projects/adrv9361z7035/ccfmc_lvds//adrv9361z7035_ccfmc_lvds.sdk/system_top.hdf @ branch origin/hdl_2017_r1

Vivado version:

tgm@asus:~$ vivado -version
Vivado v2016.4 (64-bit)
SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017
IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.


First, I have verified that the Linux is built properly by running it with the reference design provided by ADI. Long story short -- it works, kind of... At least I'm able to observe the carrier at a certain frequency on a signal analyser. The carrier is shifted by half of the sampling rate from the frequency I would like it to be. But that's not a big problem. I suspect it is due to the DDS shifting it to the edge of the spectrum.

Q1: Am I right?

The problem is when I use the custom bitstream and device tree.
I create *.dts file from system.hdf file using Xilinx's HSI tool and then add to it:
1. AD9361 related entrance under the spi0 node (copied from device tree I have found in the Linux kernel source tree in arch/arm/boot/dts/zynq-picozed-sdr2.dtsi)

2. Some 40 MHz clock related to AD9361 (I suppose...) also found in the kernel sources, i.e.,

/ {
    clocks {
        xo_40mhz_fixed_clk: clock@0 {
            #clock-cells = <0>;
            compatible = "adjustable-clock";
            clock-frequency = <40000000>;
            clock-accuracy = <200000>; /* 200 ppm (ppb) */
            clock-output-names = "XO_40MHz";
        };
    };

    ad9361_clkin: ad9361-refclk-gpio-gate@0 {
        #clock-cells = <0>;
        compatible = "gpio-gate-clock";
        clocks = <&xo_40mhz_fixed_clk>;
        enable-gpios = <&gpio0 105 0>; /* Set to 1 for extern AD9361_CLK (J1 on PZSDRCC-FMC) */
        clock-output-names = "ad9361_ext_refclk";
    };
};

3. This (to, I hoped, enable AD9517):

/ {
    clocks {
        ad9517_ref_clk: clock@3 {
            #clock-cells = <0>;
            compatible = "fixed-clock";
            clock-frequency = <25000000>;
            clock-output-names = "ad9517_refclk";
        };
    };
};

&spi0 {
    clk_ad9517: ad9517@1 {
        #address-cells = <1>;
        #size-cells = <0>;
        #clock-cells = <1>;
        compatible = "ad9517-3";
        reg = <1>;
        spi-max-frequency = <10000000>;
        clocks = <&ad9517_ref_clk>, <&ad9517_ref_clk>;
        clock-names = "refclk", "clkin";
        clock-output-names = "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7";
        firmware = "pzsdr-fmc-ad9517.stp";
    };
};

I have provided "pzsdr-fmc-ad9517.stp" firmware by building the Linux with:

CONFIG_EXTRA_FIRMWARE="pzsdr-fmc-ad9517.stp"
CONFIG_EXTRA_FIRMWARE="firmware"

I'm not sure if the second option is required, but the board behaves the same if when I changed the firmware to ad9517.stp.


I also tried to adding this (to enable cf-ad9361-dds/lpc):

&amba_pl {
    cf_ad9361_adc_core_0: cf-ad9361-lpc@43c00000 {
       //compatible = "adi,axi-ad9361-6.00.a";
       compatible = "xlnx,axi-ad9361-1.0";
       reg = <0x43c00000 0x6000>;
       dmas = <&axi_dma_rx 0>;
       dma-names = "rx";
       spibus-connected = <&adc0_ad9361>;
    };
    cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@43c04000 {
        //compatible = "adi,axi-ad9361-dds-6.00.a";
        compatible = "xlnx,axi-ad9361-dds-1.0";
        reg = <0x43c04000 0x1000>;
        clocks = <&adc0_ad9361 13>;
        clock-names = "sampl_clk";
        dmas = <&axi_dma_tx 0>;
        dma-names = "tx";
    };
};

I've changed the compatible string (but it didn't work with any of them) and addresses from 0x7902{0,4}000 to 0x43c0{0,4}000. This is because I noticed in the pl.dtsi file generated by Xilinx's HSI tool this:

amba_pl: amba_pl {
    // Other stuff...
    axi_ad9361: axi_ad9361@43c00000 {
        compatible = "xlnx,axi-ad9361-1.0";
        reg = <0x43c00000 0x10000>;
    };
    //...
};

Regarding the DMA, we use the one that is provided by Xilinx (this is what appears in Vivado after generating project from Matlab/Simulink), mainly that's what can be found in pl.dtsi (generated by HSI):

amba_pl: amba_pl {
    // Other stuff...
    axi_dma_rx: dma@40400000 {
        #dma-cells = <1>;
        clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
        clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
        compatible = "xlnx,axi-dma-1.00.a";
        interrupt-names = "s2mm_introut";
        interrupt-parent = <&intc>;
        interrupts = <0 29 4>;
        reg = <0x40400000 0x10000>;
        xlnx,addrwidth = <0x20>;
        xlnx,include-sg ;
        xlnx,sg-length-width = <0x12>;
        dma-channel@40400030 {
            compatible = "xlnx,axi-dma-s2mm-channel";
            dma-channels = <0x1>;
            interrupts = <0 29 4>;
            xlnx,datawidth = <0x40>;
            xlnx,device-id = <0x0>;
            xlnx,include-dre ;
        };
    };
    axi_dma_tx: dma@40410000 {
        #dma-cells = <1>;
        clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk";
        clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>;
        compatible = "xlnx,axi-dma-1.00.a";
        interrupt-names = "mm2s_introut";
        interrupt-parent = <&intc>;
        interrupts = <0 30 4>;
        reg = <0x40410000 0x10000>;
        xlnx,addrwidth = <0x20>;
        xlnx,include-sg ;
        xlnx,sg-length-width = <0x12>;
        dma-channel@40410000 {
            compatible = "xlnx,axi-dma-mm2s-channel";
            dma-channels = <0x1>;
            interrupts = <0 30 4>;
            xlnx,datawidth = <0x40>;
            xlnx,device-id = <0x1>;
            xlnx,include-dre ;
        };
    };
};

 

What I've got when I use ADI's reference design and what I want to see (do I?) with custom desing & device tree during boot-up is somethin like this:

ad9361 spi32766.0: ad9361_probe : enter
...
ad9361 spi32766.0: ad9361_probe : AD936x Rev 2 successfully initialized
ad9517 spi32766.1: AD9517 successfully initialized
cf_axi_dds 79024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x79024000 mapped to 0xf09cc000, probed DDS AD9361
...
cf_axi_adc 79020000.cf-ad9361-lpc: ADI AIM (10.00.b) at 0x79020000 mapped to 0xf09d8000, probed ADC AD9361 as MASTER

What I've got instead is:

ad9361 spi1.0: ad9361_probe : enter
...
ad9361 spi1.0: ad9361_probe : AD936x Rev 2 successfully initialized
ad9517 spi1.1: Unrecognized CHIP_ID 0x0

Questions:
Q2: Do I need to make AD9517 work before making cf-ad9361-* working?
Q3: If so, how can I make AD9517 to work?
Q4: Why does AD9517 not work? I found this thread: https://ez.analog.com/thread/101995-cfaxiadc-not-appearing-in-dmesg but I'm not sure how to approach the problem
Q5: Is it possible to get the equivalent boot-up log as in the case of the reference design?
Q6: Can cf-ad9361-dds/lpc work with Xilinx provided DMAs? How to make them visible?
Q7: Should I add other stuff that can be found in arch/arm/boot/dts/zynq-picozed-sdr2-fmc.dts or arch/arm/boot/dts/zynq-picozed-sdr2.dtsi? For example, qspi node? Or maybe it is not needed?


Q8: I did not add to my device tree clock@2 (labelled usb_ulpi_fixed_clk) and usb-ulpe-gpio-gate@0 (labelled usb_ulpi_clk) -- both are in arch/arm/boot/dts/zynq-picozed-sdr2.dtsi. I assumed these are not relevant. Am I right? Or maybe I should include these nodes?


Q9: Is `#include <dt-bindings/inpu/input.h>` (which subsequently includes linux-event-codes.h) relevant? Maybe I should build the device tree inside the Linux kernel instead of using what is returned from HSI & system_top.hdf tandem?


Q10: Is it enough to disable DDS in Vivado by setting DAC_DDS_DISABLE to 1 in AXI_AD9361 config? Can it be done somehow using software, e.g., libiio? (Assuming I can see cf-ad9361-dds-core-lpc and cf-ad9361-lpc when inspecting /sys/bus/iio/devices/.)


Additional logs/messages:

root@xxx:~# cat /sys/bus/iio/devices/iio\:device*/name
ad9361-phy
xadc

Outcomes