I have developed a design that use the Xilinx FPGA ultrascale “XCKU040-FFVA1156” that interface the ADC (AD9694) by using 4 lines JESD.
The JESD line rate is > 4 Gbps.
The FPGA design is implemented using VIVADO 2018.1 and the Xilinx IP JESD204 PHY Version 4.0
I have the following situation:
- If the analog signal input to the ADC is in the range 70mVpp all is working correctly: the FPGA generate the signal “rx_sync” that stay permanently deasserted (high) and the digital data transmitted to the ADC are correctly received
- If the analog signal input to the ADC is greater than 70mVpp (i.e.: 100mVpp) are detected from the FPGA “Disparity Errors” and consequently asserted the signal “rx_sync” (low) and the reception of data interrupted
(continuously I have: a new synchrnonization restart => rx_sync deasserted => data received correctly followed to data with “disparity errors” detected => rx_sync asserted => new synchronization ….)
The above situation is present both with scrambler enabled or disabled.
Can you help me to solve this problem ?
Many thanks for your collaboration