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Reduce RF synth filter BW, improve LO short-term stability

Question asked by Peter-S on Jul 11, 2018
Latest reply on Jul 11, 2018 by Vinod

Custom modem, Tx from one AD9364 chip at RF frequency 1.2GHz, Rx on a different AD9364 chip ; below plot shows the frequency offset (the difference between tx and rx RF frequencies) estimated by the receiver, sampled every 6ms over a 10s observation period.


The rate of variation in [(Chip1 Tx LO) - (Chip2 Rx LO)] of [50 Hz in <0.5s] [ie 100Hz/s at 1.2Ghz] is more than can be attributed to drift in the reference clocks (both 40MHz) going into each AD chip (which is no more than 1ppb per second).


=> I want to try reducing the RF PLL tx/rx synthesizer loop filter bandwidth


1) I don't see any driver API or init_param support to modify RF synth loop bandwidth. Based on the downloadable .txt files for the synth LUT tables (v3) [matching the tables built into the driver code] it appears that the driver uses a fixed loop bandwidth of 250kHz over all VCO (and hence LO) frequencies [both my chips in FDD mode].


2) The loop filter component identification in this datasheet diagram is incomplete



Is it a correct guess that C1/C2/C3 goes left to right above, and R1/R3 goes left to right above ?


3) There is no indication on datasheet of the capacitance/resistance values (F/ohms respectively) that correspond to the possible register config values (0-15) for C1/C2/C3/R1/R3. Can AD provide this so that customer can simulate the loop filter frequency response themselves for given register settings ?


4) How to practically go about reducing the loop filter BW ?

[yes, officially this forum prefers not to comment on SPI registers (but...there is no support above API for this), and yes, datasheet says 'use the driver and use the provided LUTs (built into driver) and don't change anything' (but...this is a practical performance issue for higher order modulations and lower symbol rates), and yes any modification is at my own risk over temperature etc)  ... so can some exception be made to advise on this topic as the programmable loop filter seems such a nice feature of the silicon so it seems a shame if there is no way for user to take advantage of it ? ]


5) Any other advice for improving the LO frequency short-term stability ? Eg I can try changing the charge pump current to change the loop gain (can accept longer lock times) but its the same issue ; there is no information about the current setting vs the loop gain, and no support for adjusting the loop behaviour above the API ?


Many thanks