AnsweredAssumed Answered

AD9528 PLL2 can not locked

Question asked by yeaten on Jul 11, 2018

Hi,

We are developing a board based on ADRV9371-W/PCBZ, but we couldn't achieved to lock PLL2. Here are the similarities/differences:

  1. PLL1 is powered down, we are using in holdover mode. There is 122.88Mhz TCXO is supplied to VCXO_IN_P/N by DC coupled differential LVDS with external 100 ohm diff termination . REF inputs are floating as in ADRV9371 and REF_SEL is tied to GND. VCXO_VT and LF1 are floating as we are using TCXO instead of VCXO.
  2. VDD pins for used output buffers are tied to 3V3 and VDD pins for unused output buffers are floating(There is no info about it in the datasheet?).
  3. VDD pins (1, 10, 16, 20 and 72) are tied to 3V3 through EMI filter.
  4. LF2 are same as in ADRV9371 (1nF/470nF)

Here is the SPI write sequence:

  • 0x000 - 0x3C
  • 0x001 - 0x80
  • 0x100 - 0x01
  • 0x101 - 0x00
  • 0x102 - 0x01
  • 0x103 - 0x00
  • 0x104 - 0x04
  • 0x105 - 0x00
  • 0x106 - 0x80 - Force holdover
  • 0x107 - 0x00 - CP1 are tristate
  • 0x108 - 0x81 - Diff VCXO active
  • 0x109 - 0x00
  • 0x10a - 0x02
  • 0x10b - 0x00
  • 0x200 - 0xE6 - Same as ADRV9371
  • 0x201 - 0x87 - feedback divider is 32, we have also tried 30(0x08) with M=3 and N2=10
  • 0x202 - 0x03
  • 0x203 - 0x01
  • 0x204 - 0x03
  • 0x205 - 0x2A - Same as ADRV9371
  • 0x206 - 0x00
  • 0x207 - 0x00
  • 0x208 - 0x09
  • 0x209 - 0x00
  • 0x300 - 0x329 are set.
  • 0x32A - 0x32E are all 0x00
  • 0x400 - 0x00
  • 0x401 - 0x00
  • 0x402 - 0x98
  • 0x403 - 0x80
  • 0x404 - 0x04
  • 0x500 - 0x14 - PLL1 is powered down even if we activated force holdover.
  • 0x501 - 0x6F - Ch(4-7-8-11-13) are used.
  • 0x502 - 0x16
  • 0x503 - 0x90 - Ch(4-7-8-11-13) are used.
  • 0x504 - 0xE9
  • 0x505 - 0x0A
  • 0x506 - 0x00
  • 0x507 - 0x04
  • 0x00F - 0x01

and 0x508 status is 0x10 and 0x509 status is 08.

 

What we have tried:

  • When we tried the same thing in ADRV9371 PLL2 is always locked if the M and N2 dividers are set to proper frequency for VCO, even if CP current(0x200) is set to min and max values.
  • VDD pins for unused output buffers are AC coupled to GND by 100nF.
  • We forced CP of PLL2 to pump-down and pump-up mode, 0V and ~1.80V were measured respectively.

Do you have any advice what is the problem?

Thanks,

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