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ADF4108 Jitter Issue

Question asked by Rykken on Jan 3, 2012
Latest reply on Jan 12, 2012 by icollins

I am trying to resolve a jitter/FM issue with a set of frequency up and down converters.  Each of these converters use "2" separate ADF4108's to phase lock VCO's in a dual conversion heterodyne process.  The VCO's are used as Local Oscillators, the first VCO is a Hititte PN:HMC390 phase-locked to 3770MHz and is mixed with a 70MHz IF to generate the internal 1st IF at 3700MHz.  The 2nd VCO is a Hititte PN:HMC586 and in this application is tuneable from 4 - 6.7GHz.  The 3700MHz is mixed with the 4 - 6.7 GHz LO to provide a tuning range of 300 - 3000 MHz.

 

- The reference is a Silicon Labs SI-550 operating at 840 MHz and is divided down to 120 MHz.  This 120 MHz is applied to the ADF4108's reference input and is further divided down to 5 MHz which also sets the PFD to 5 MHz.

 

- The PLL's and VCO's each have their very own Linear Technologies regulator PN: LT1962.

Note: The ADF4108 Vp and Cp are supplied from the same regulator at 3.3VDC, the two supply lines have Amercian Technical Ceramics PN:ATC550L broadband decoupling capacitors.

 

- The grounding system is continuous for all circuits.

 

The test set when looped back is perfect and produces a constellation with extremely sharp decision points.  When passed through these converters however, the following is observed using a 64 QAM Signal:

 

     Baud Rate = 1 MBaud results in BER of 1e-5 or worse and obvious rotational smearing in the constellation.

     Baud Rate = 15 MBaud results in BER of 1e-11 typical with minimal rotational smearing in the constellation.

     Baud Rate = 20 up to 42 MBaud results in error free BER performance without any observable rotational smear in the constellation.

 

What I have tried in an attempt to isolate the cause of the apparent residual Jitter/FM.

 

1). I have tried several loop designs using ADIsimPLL with only minor improvements in the performance.

2). Increased the Cp current to 8 mA with minor improvement.

3). Substituted a Wenzel SC-Cut temperature stabilized OCXO in place of the SI-550 with absolutely no change in performance.

4). Substituted Lab Power Supplies in place of products internal switching power supplies without improvement.

5). Isolated the switching power supply grounds from the converter grounds without improvement.

6). Changed the PFD frequency from 5 MHz down to 1 MHz and expected things to get worse but only observed phase noise increase on the spectrum analyzer and BER performace nearly identical.

7). Added additional decoupling capacitor directly on the VCO power pins, no change observed.

 

There is residual Jitter/FM somehow modulating the VCO's beyond the control of the PLL Loop.  I have been unable to isolate it or come up with a solution to eliminate it.

 

Any advice or ideas would be greatly appreciated.

Thank you

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