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JESD204 Interface Framework - Eye scan

Question asked by modimo on Jul 10, 2018
Latest reply on Jul 18, 2018 by modimo

Hello,

I have successfully applied JESD204 Interface Framework on my board with ad9695 ADC. I have ADI IIO Oscilloscope up and running. For linux I am using Analog devices brqanch master-4.14. 

physical and link layer drivers:

axi_adxcvr - adi,axi-adxcvr-1.0

axi_jesd204_rx - adi,axi-jesd204-rx-1.0

And my question is how can I perform eyescan? It seems that axi_adxcvr hdl component has eye scan capability, but corresponding linux driver does not has support for it. I noticed that adi,axi-jesd-gt-1.0 driver has eye-scan capability but is otherwise not compatible with di,axi-jesd204-rx-1.0.

What drivers and configuration should I setup to perform eyescan?

Relevant DTS:


axi_adxcvr_0: axi_adxcvr@80000000 {
compatible = "adi,axi-adxcvr-1.0";
//compatible = "adi,axi-jesd-gt-1.0";

reg = <0x0 0x80000000 0x0 0x10000>;
clocks = <&clk0_adc_clk>, <&clk0_adc_ref_clk>;
clock-names = "conv", "div40";
#clock-cells = <1>;
clock-output-names = "adc_gt_clk", "rx_out_clk";
adi,sys-clk-select = <3>;
adi,out-clk-select = <4>;
adi,use-lpm-enable;
};

axi_jesd204_rx_0: axi_jesd204_rx@80010000 {
compatible = "adi,axi-jesd204-rx-1.0";
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80010000 0x0 0x10000>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
clocks = <&clk 71>, <&axi_adxcvr_0 1>, <&axi_adxcvr_0 0>;
adi,octets-per-frame = <1>;
adi,frames-per-multiframe = <32>;
#clock-cells = <0>;
clock-output-names = "jesd_adc_lane_clk";
};

Link status:

# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane0_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 23 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 0, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x62, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane1_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 25 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 1, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x63, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane2_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 26 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 2, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x64, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/lane3_info
CGS state: DATA
Initial Frame Synchronization: Yes
Lane Latency: 2 Multi-frames and 25 Octets
Initial Lane Alignment Sequence: Yes
DID: 0, BID: 1, LID: 3, L: 3, SCR: 1, F: 0
K: 31, M: 1, N: 15, CS: 0, N': 15, S: 0, HD: 1
FCHK: 0x65, CF: 0
ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 0
FC: 6000000
# cat /sys/devices/platform/amba_pl/80010000.axi_jesd204_rx/status
Link is enabled
Measured Link Clock: 149.780 MHz
Reported Link Clock: 150.000 MHz
Lane rate: 6000.000 MHz
Lane rate / 40: 150.000 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No

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