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AD9172 custom design mismatching jesd204 parameters

Question asked by LCr on Jul 10, 2018
Latest reply on Jul 17, 2018 by LCr

Hi,

 

I'm currently developing a project based on the AD9172. For that purpose, I bought one eval board and the ADS7v2.

They work correctly together and now I want to use another FPGA board (the ZCU102), so I designed a simple FPGA project based on the JESD204 IP from Xilinx.

 

I want to use JESD204 mode 2 (3 lanes). I configured the IP like this (IP core shared in design):

I program the FPGA and then I set the DAC with ACE like this:

I must change some registers because my clocking scheme is the following:

For the AD9172:

Registers

Value

Comments

0x308

0x8

physical lane 0 correspond to logical lane 0, phy 1 to log 1 etc.

0x309

0x10

0x95

0x0

Enable PLL

0x790

0

Required

0x791

0

Required

0x796

0xE5

Required

0x7A0

0xBC

Required

0x794

0x08

Recommended CP current

0x797

0x10

Required

0x797

0x20

Required

0x798

0x10

Required

0x7A2

0x7F

Required

Pause 100 ms

0x799

0xC3

Output clk = dac clock /4, N div=3

0x793

0x18

Input divider = 1

0x94

0x00

DAC clock = VCO / 1

0x792

0x2

Reset VCO

0x792

0

Pause 100 ms

0x7B5

READ

If locked, equals 1

For the HMC7044:

Registers

Value

Comments

3

0x2C

Disable PLLs

5

0x6F

CLKIN1 as external VCO input

0x64

0x1

External VCO

0xED

0

CLKOUT3 output mux = channel divider

0x151

0

CLKOUT13 output mux = channel divider

0x14B

0x40

CLKOUT13 divided by 64 -> 500 / 64 = 7.8125 = sysref to FPGA

0x14C

0

0xE7

0x40

CLKOUT3 divided by 64 -> 500 / 64 = 7.8125 = sysref to DAC

0xE8

0

0xE3

0

CLKOUT2 output mux = channel divider

0x147

0

CLKOUT12 output mux = channel divider

0xDE

0

CLKOUT2 divided by 2 -> 500 / 2 = 250 = data rate clock unused because external dac clock

0xDD

0x2

0x142

0

CLKOUT12 divided by 2 -> 500 / 2 = 250 = data rate clock to FPGA

0x141

0x2

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