we have an AD6676 and a VC707 Xilinx FPGA eval board. As a simple start of working with the Analog Devices JESD204B Framework, we wanted to run the example design using the No-OS Software. We ended up with seeing a Capture Error from adc_ramp_test function, which complains about only receiving zeros.
I therefore added some debug signals to the block design to see what's going on. Turned out that there is some data coming in through the Gigabit Tranceivers but I hardly can interpret the data.
I can see the ILA at the beginning with an R as the first Byte and A as the last Byte of a multiframe. Afterwards the data looks quite random to me. It doesn't seam like the expected counter of the ramp_test. After a while sync~ and reset~ get asserted again, which I would expect not to happen.
I would highly appreciate any advice on this one. Is this behavior known or even expected? What could possibly be the issue? Why does the ax_ad6676_core doesn't output any data?
Thanks in advance,