I would like to use AD9528 as a buffer. The question seems to be answered here:AD9528 devclock/SYSREF distribution of multi-chip use case
In my case, I have a stable clock (recovered from eCPRI/PTP) and a stable SYSREF. The device clock is fed to the VCXO input pins and the SYSREF is fed to the SYSREF input pins. Both REF_A and REF_B are left unconnected and PLL1 and PLL2 are bypassed. Is my understanding correct?
For JESD synchronization, it is required to meet setup and hold timing of the SYSREF signal. In my case, is there any such requirement at the SYSREF input?