Our company is currently developing a high-end system based on the AD9172 and AD9208. To speed up the design, we decided to bought your dev boards for each component and also an FPGA board.
I’m busy with the AD9208. I use the AD9208-3000EBZ and the ADS7v2 for that purpose.
I try to correctly configure the ADC thanks to ACE but it seems there’s some bugs in the soft.
I already know that the capture limit is really below the memory’s one. But I have a work around for that, at least for now.
What the system requires is described on the following figure:
As I understand the datasheet, I should be able to configure the chip like this:
I’m sampling two signals at 3GHz : I and Q. Both are baseband signals, bandwidth = 250MHz. I want to reduce the transmission rate because my bandwidth is only 250MHz.
So I need to use one DDC. First input is channel A (I) and second one is channel B (Q).
Because my signal is already baseband, I set the NCO to ZIF mode (bypassed).
Then I want to decimate by two, while keeping both I and Q at output (no complex to real block).
So I set filters as follows: HB1_HB2_complex.
I finally want the send them via JESD204. Because I want I and Q, I set number of converters to 2.
I want 8 lanes to reduce the lane rate; the rate is 3.75GHz and the refclock is 187.5MHz.
However when I try to capture, I either get nothing (ACE hangs) or get wrong signal.
I think I should see two signals (I and Q or ch A and ch B) on the Analysis window, am I wrong? I only see one and the spectrum is not correct.
Thus I am asking the following questions:
- Could you confirm that I need to supply 187.5MHz on J3 of ADS7v2?
- Is my understanding of the chip correct?
- Is there in my configuration something wrong?
- What does ACE do with the received signals from JESD204: if two converters, why is there only one?
Thank you in advance