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the pll of bf533

Question asked by go_go_go on Jul 9, 2018
Latest reply on Jul 9, 2018 by Jithul_Janardhanan

I design a BF533SBBCZ400 board, when i test it by ADSP 5.0, i found that:




1.when i want to make the PLL  frequency multiplication effective. Firstly,i have to switch to active mode,

and then i have to switch to FULL_ON mode.



2.After executing the program under the ACTIVE mode, it must be recompiled and loaded by the emulator to make the previous settings take effect.


After that,the core clock will change. 


When i test it , i find that  the total current consumption due to the internal core circuitry is too small . For example, in an application with VDDINT at 1.2 V and a high-performance Blackfin processor at a TJ of +25oC, the corresponding IDDINT for the VDDINT power domain would be approximately 75 mA. Bf533 processor is not working properly.

I think it may be the hardware problem, but i don't know how to find it. 


The following is the schematic part of my board:




The following is the PCB part of my board: