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HMC983 output clock cycle

Question asked by pohchuan.leng on Jul 8, 2018
Latest reply on Jul 9, 2018 by dyoung1

We intend to set a divide factor as an example (64+1/1024) with input frequency roughly 5GHz.  How will the output look like?  Will it have 1023 clocks with same width and one clock with shorter width?  Or will the sigma-delta modulator in the chip adjust the phase such that all clock cycles at the output look symmetrical?