We intend to set a divide factor as an example (64+1/1024) with input frequency roughly 5GHz. How will the output look like? Will it have 1023 clocks with same width and one clock with shorter width? Or will the sigma-delta modulator in the chip adjust the phase such that all clock cycles at the output look symmetrical?

The delta sigma modulator will adjust every clock cycle such that the average divider value is 64+1/1024. The maximum N adjustment per cycle is +4/-3 (68 to 61).