I met some problem when solving Multi-HMC7044 sync.
1.Two HMC7044 local at different boards.
2. 100MHz Ref Clock comes from the same source, so do sync pulse.
3. SYNC pulse, 1us pulse width, 1ms period.
4. HMC7044 outputs 1.6GHz DCLK to ADC, and SYSref=1MHz.
my doubts as below:
/A. If PLL1 used, Any use of divider IN1,R1,R2, will cause sync failure, phase relationship will change after each reboot. If all divider set to bypass, SYNC is OK. From my view, HMC7044 can't be designed to this-divider can’t be used when syncing.
/B. I gave up PLL1, and input ref to OSCIN directly. I found SYNC is not so stable according to later experiment. Two ADC clocked by each HMC7044, They run at 1.6Gsps and sample the same 400MHz CW signal. I calculated the phase difference of two sample result, most of time phase difference is -8°, which comes from the cable and it's acceptable. Occasionally, phase difference jumps to -120°，that really weird，because one sample mean 90°，How can 120° occurs？ In this situation, HMC7044 still locked up.
So any advice?