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AD9528 clock distribution circuit

Question asked by kangyunwss on Jul 6, 2018

JESD204B & CPRI Clock distribution



I am designing JESD204B interface between AD9375 and Xilinx FPGA. 

Xilinx FPGA has CPRI interface to another device. 

At first, the FPGA receive 122.88MHz clock from AD9528 and use it as reference clock for CPRI interface. The CPRI serdes recovered clock make PLL locked clock(30.72MHz) and provide it to AD9528 as its reference clock(REF A input.)  

The AD9528 uses the REF A input as reference clock and control VCXO for synchronization. 

AD9528 provides the DEV_CLK and SYSREF_CLK for AD9375 as JESD204B interface clock which are generated from PLL in AD9528 with VCXO and REFA input.


Would you let me know whether this clock tree fine to implement both JESD204B interface and CPRI interface on FPGA?

If there is any recommendation for this circuit, give me the advice. 



Kangyun Cho