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Question asked by jlally on Jul 6, 2018
Latest reply on Jul 11, 2018 by srimoyi

For the AD9371, in UG992 Figure 49 shows a Ts= +2.5ns at the pins results in a Ts = +0.5ns at the core.    I think this means that the SYSREF transition is 2ns closer to the Rising Edge of DEV_CLK at the core than at the pins, correct?  If correct then it seems SYSREF must have taken 2ns longer to reach the core than DEV_CLK, (i.e. SYSREF was 2.5ns ahead of DEV_CLK at the pins now at the core SYSREF is only 0.5ns ahead of DEV_CLK, therefore SYSREF must have been delayed 2ns more than DEV_CLK to get from the pins to the core).   Yet, there’s text in Figure 49 “CLK DELAY= 2ns”, and a buffer symbol with text above it that reads “DEV_CLK DELAY IN REFERENCE TO SYSREF”.   Is DEV_CLK really delayed by 2ns with respect to SYSREF from pins to core, or is it the other way around as I’ve described?    If DEV_CLK is delayed by 2ns more than SYSREF can you please explain how that results in a decrease in Ts from pins to core (+2.5ns to 0.5ns)?  Need to get length matching correct on our PCB and need to make sure we don’t do exactly the wrong thing…