I've implemented a custom "high-level" driver for DMAC IP core with zero-copy from FPGA to userspace, that uses dmaengine and "low-level" dma-axi-dmac driver underneath. If a timeout happens while reading data from fpga (e.g. my dsp core stopped producing new samples in the middle of receiving), dmaengine_terminate_all is called. The transmission is stopped, but I'm afraid some data is left in the DMAC internal fifo, and if a new transaction is started, this data will come out first.
I've looked inside axi_dmac_terminate_all and there only axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0); is called, which simply pauses the operation, but does not reset anything.
Am I missing something and the internal fifo is in fact reset before a new acqusition, or, if not,how it can be fixed?