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Modifying Verilog in axi_ad9361 for Tx/Rx

Question asked by TimSteinb on Jul 5, 2018
Latest reply on Jul 11, 2018 by larsc

Hi, I am attempting to modify the Verilog code in the HDL for the axi_ad9361, and am trying to add some code that would occur either before a message is sent, or after a message is received. The axi_ad9361_tx case seems relatively straight forward, since dac_data is configured as an output, however the adc_data in the axi_ad9361_rx file is configured to be an input for some reason. Essentially I will be running a hashing algorithm on the data being sent and received, so in the case of sending a message I can just take the data being sent directly, but I'm not sure what I would be messing with in the receive case.

 

Can someone just give me a high level rundown of what the code is doing in axi_ad9361.v, axi_ad9361_rx.v, axi_ad9361_tx.v, axi_ad9361_rx_channel.v, and axi_ad9361_tx_channel.v so that I can figure out where I need to add my code?

 

axi_ad9361 plutosdr

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