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ADF4356 fails to lock to 2.4 GHz and settles at 2.38 GHz.

Question asked by rodneyc76 on Jul 5, 2018

I am using an ADF4356 with a 200 MHz reference clock on a custom board (based on the corresponding EV-ADF4356SD1Z (Rev. A) reference board design.) The eval board works without issues, although I have only used the 122.88 MHz on-board crystal. 

Muxout/LockDetect is low is my primary check for lock. I have tried different settings in Register 7 e.g. LD Mode, with no luck.


If we use a passive RF probe to look at the output, we see approximately 2.38 GHz output with -10 dBc spurs at ~200 kHz offsets. Probing Vtune shows a sawtooth waveform with 100 mVpp and similar 200 kHz repeat rate. None of the spurs seem to be above 2.4 GHz so it suggests that the VCO tuning of the cap bank is a little high. Vtune averages 4.5V (while we observed around ~2V on the eval board). 


I am not sure where the 200 kHz rate appears from and I am wondering how the Autocal behaves. Could this create updates at this rate? 


Is there a way to manually set the VCO core and 8-bit sub-band?


The datasheet describes Vref (pin 23) "Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground plane as close to this pin as possible". We measure 4.2V here, which seems much higher than the middle of the tuning range (unless it's nonlinear). 


We have ensured that Ndiv and Rdiv are not connected to the mux when trying to lock. But have confirmed that they look correct (but incorrect frequency for Rdiv confirming lack of lock). 


Our only lead at the moment is that the load of the PLL is preventing lock (somewhere between VCO cal and enabling output dividers and drivers), but we find ourselves asking several questions about what is happening internally, and could use some advice.








Typical settings obtained from the ADF4356 software



Seems to be related time between Chip Enable and SPI programming. Chip enable goes high at power-on now, and programming happens by user trigger. 


What is the minimum wait time for the ADF4356 to be stable after Chip Enable goes high? I don't see a spec in the datasheet. 


I have also changed the initialization to program with Autocal on, but then turn off all Autocal, ADC conversion, and ADC Enable after 2ms. I suspect it was more to do with Chip Enable delay.