I am writing for support of ADATE320 and ADATE209.
In our project, ADATE320 is uesd to realize 1.6 Gbps LVDS signal adjust.
Original LVDS signals comes from FPGA (Xilinx HP bank). There is my first
question, could you give us a circuit of typical application ?
And we want to increase data rate from 1.6 Gbps to 2.5 Gbps ,or 3.2 Gbps.
We get imformation from ADATE209 datasheet shows that ADATE209 will
meet our application requirement. But we can't understand how it works. Could you
help us about this?