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Generate Design wrapper like ADI

Question asked by NilsMinor on Jul 5, 2018
Latest reply on Jul 10, 2018 by NilsMinor

Hello,

 

I am trying to port the reference design of daq2 to a custom fpga board using only the AD9234 ADC.

The manufacturer gave me all files of the pga board (xdc, block design and top_level) for starting. The top_level is an vhdl file which I like to change in order to use verilog. My question is what is the design flow of Analog devices when creating a new design. 

 

Do you start by making the over all block design (you call it system) generating the system_wrapper and then writing your system_top.v ? And how do you create the wrapper for the system in verilog? Vivado only gave me the option to generate an hdl wrapper.  Or did you write the system_wrapper by your self? Could you please tell me a bit more about your design flow so I could adapt it in order to develop my design in the way ADI would do it?

 

* Update: I noticed I need to change the project language to verilog in order to get a verilog wrapper  but I am still interested in the design flow

 

Many thanks,

Nils

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