AnsweredAssumed Answered

Dual AD2S1210 on SPI bus

Question asked by ianstedman on Jul 4, 2018

I am working on a system that uses 2x AD2S1210 devices connected via a SPI bus to a NXP MPC5674 Microcontroller. We are having some intermittent issues with corruption of data read from the device. I have been asked to review the usage of the device and upon reading the manual, I'm a bit confused.

 

In the serial interface section of the datasheet, it states:

 

The falling edge of WR/FSYNC takes the SDI and SDO

lines out of a high impedance state. A rising edge on WR/FSYNC

returns the SDI and SDO to a high impedance state. The CS input

is not required for the serial interface and should be held low.

 

Now in our system, we have 2 x chip-selects, one per AD2S1210 and a shared WR/FSYNC signal. Reading the manual, it would suggest that in my system, when WR/FSYNC is driven low, the SDO outputs of both devices will be driven, regardless of the CS input, is this correct?

 

We have got around some earlier issues by doing a dummy read from the device before getting the data required but there are still intermittent issues.

 

We permanently use the device in configuration mode, so A0 & A1 are set to logic 1. Currently we are using SPI mode 2 (CPOL=1, CPHA=0), will change this to SPI mode 3 (CPOL=1, CPHA=1), to match your Linux driver.

 

Any help appreciated.

 

Outcomes