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AD9779 DAC: SYNC_I and initialization

Question asked by Piotr on Dec 31, 2011
Latest reply on Apr 25, 2012 by Tguy

I have two questions regarding AD9779. I'm using it in a QAM modulator working at 160 Msps (28 Msymbols/s sampled 6 times per symbol). I don't use DATACLK output, the digital data going out of the FPGA is clocked with the same clock, that is applied to REFCLK input.

As I understand from the datasheet the SYNC_I should be high during positive edge of REFCLK at which data is clocked out of the FPGA. Is it correct to apply constant '1' to SYNC_I when REFCLK frequency is equal to DATACLK frequency (even with 2x or 4x interpolation enabled)?

Second question: I noticed that after initializing DAC in interpolation mode the MER of output QAM signal is different from initialization to initialization (there is 0.5-0.7 dB difference between the best and worst cases). The initialization sequence consists of hardware reset, writing 0x03 to register 0x09, 0xc0 to reg. 0x03, 0x1f to reg. 0x0a and 0x40 to reg 0x01 (2x interpolation). Then appropriate VCO band is written to register 0x08.

Is there any way to get the best case after each initialization?

By the way - I noticed that software reset didn't clear registers 0x08, 0x09 and 0x0a. Is that correct? Datasheet says that they should be reset.

Best regards,