I am currently working with the Ads7-v2ebz and AD9208-3000ebz for a unique evaluation. I have modified the FPGA image that is on the analog website (https://wiki.analog.com/_media/resources/eval/ads7-v2ebz_13052_revc_design_files.zip) and would like to have this loaded on the FPGA from the ACE software sutie rather the manually with a JTAG connection. To give an overview I’m using the ACE software suite to collect data, currently just noise, with the modified FPGA image. The FPGA image is a modified version of the AD9689_AdS7v2.xpr that is contained in the zip file I linked to above, the modification is rather simple; I’m replacing the first 8-bytes in a data packet with a custom value. There is not documentation for the FPGA project, and I’m hoping to get a better understanding of the data flow and design itself. I’ve use my best intuition after reading the HDL to make the modifications but verifying I’ve interpreted the data flow would be useful.
Currently when I load the FPGA via JTAG with my custom image the ACE software panics a little (I’m not sure if it reloads the FPGA or not either) I’ve managed to do some data collections with what I suspect to be the modified FPGA but I’m not able to the connect to the ILA to view the internal signals. So here are a few things I’d like to know about:
- Can I override the FPGA that the ACE software suite loads? So that I don’t have to load it via JTAG and hopefully this would cause fewer issues.
- Can I get more design documentation on the FPGA image for the ads7-v2ebz? The Vivado project is the AD9689_AdS7v2.xpr. I compared the chips and believe there is no issue using this image for the AD9208 but perhaps there is a project specifically for this chip.
2b. The external trigger functionality in the FPGA was a little difficult to follow so if a document doesn’t exist can we some get information on the data flow with an external trigger and how the ACE suite will collect that data?