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AD5422 register read-back bit-shifted wth 5.6MHz clock

Question asked by eugeneso on Jun 28, 2018
Latest reply on Jul 4, 2018 by eugeneso

When I read back a register value from the AD5422 using the EVAL-CN0233-50PZ development kit, the value I get is wrong, appearing to be right shifted by a single bit.  This goes away if I lower my spi clock speed from 5.6 to 2.8MHz.  Would like to understand the root of this issue.  

 

Logic screen shots are attached.  I am expecting bit 12 to be logic high as per the figure labelled "spi okay.png".  You can observe in "spi bad.png" that the device output is slightly shifted so the clock rising edge is unable to catch it.

 

Thanks

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