I'd like to request to add a /SRST "System Reset" signal on J1 of the ICE-1000, like the /TARGET_RESET on J2 pin 10. According to the ICE-1000 manual's Figure 1-4, there are a couple of NC pins (4 and 5) on J1 that would allow that. According to Al Clark and Kempler Itamar's helpful question and answers for "New JTAG Connections (10 pin)", I found the description of J2's /TARGET_RESET to match this functionality, so it's already on the ICE-1000. However, it's not clear whether it's an Open-Drain/Open-Collector output signal the emulator can ground to hold the entire target system in reset. Obviously, the target's reset signal must also be OD/OC to both to coexist.
I've used this functionality with other Debuggers/Emulators and it's quite useful, e.g. loading SRAM with code or data before releasing reset.