I have a question about how the signal monitor bits are mapped into the JESD lanes if you have more than one converter.
Where do the signal monitor bits come out, Do A and B come out at the same time or do you have to have a SPI write to select which one comes out. Do the bits come out only in lane 0 or multiple lanes? If the data come out multiple lanes is it duplicated across the lanes so that lane 0, 1, ... all have the same signal monitor information at one time? Or will A come out some lanes and B out others.