I am puzzled by the datasheet of AD2S1210, in the serial interface section.
I read: "The CS input is not required for the serial interface and should be held low." but at the same time, the CS input is appearing in the timing figures Figure 33, 34 and 35 with associated timing constraints t1, t2 and t31.
As I am programming an interfacing device in a fpga, I am wondering if I can hold CS low as indicated, and what is the meaning of timing constraints, especially t1 (changing A0 and A1) in this case?
Do I need to release CS when changing A0 and A1?