We have developed a custom board using a BF70X part. I have the SPI working but it always shuts down before the last byte is finished being sent out when monitoring the status of the FIFO TX buffer. The FIFO is empty, but that last byte is still getting shifted out in the shift register when the SPI gets shut down.
I tried using the SPIF bit as the documentation says "The SPI_STAT.SPIF bit indicates that a single word transfer is complete" The documentation also says "To maintain software compatibility with other SPI devices, the SPI_STAT.SPIF bit is also available for polling." But this bit never changes. It is always 1. Is this a Silicon defect?
So I have 2 related questions.
1. Is there a way to clear the SPIF bit so that it actually reflects 0 during a transfer and 1 when it is finished?
2. If not how can I monitor when the SPI has finished sending out that last byte.
Obviously I could hack something together to put a delay on that last byte before shutting down the SPI, but that is poor coding and I want to avoid it at all costs if possible.