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Costum HDL Design Clock Dedicated Route Error

Question asked by Quamstar on Jun 26, 2018
Latest reply on Jun 28, 2018 by larsc



we have developed a board with reference to the FMCOMMS5-EZB and the ZC702. We had to modify the XDC file of AD reference design and route the signals do different pins. We did that straight for other signals and then modified the system_top as well. When running the synthesis and implementation we receive the following error:


[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/clk_ibuf_s] >


    i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/i_rx_clk_ibuf (IBUFGDS.O) is locked to IOB_X1Y64
     and i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/i_clk_gbuf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31


Honestly, this is something i don't know how to handle. Adding the set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/axi_ad9361_0/inst/i_dev_if/i_clk/clk_ibuf_s] into the xdc file results into an successfully implementation, but with errors in timing. These errors are in the rx_0_clk to clk_fpga_0 and rx_0_clk to rx_1_clk and i'm quite sure that this will be an issue in the end (I did not tested it so far). Does anyone could support us with the error above?


Thanks and kindy regards



P.S.: See attached the related XDC file and system_top.v