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AD9361 Reference Design processing speed delay

Question asked by fpgageek on Jun 25, 2018
Latest reply on Jun 25, 2018 by fpgageek

Hi, One of your colleagues Dragos has told us to post this question here as "It might be a limitation of a data bus".

Our problem/Question  goes as follows:

We have successfully implemented two buffers (PING PONG) by extending  your given streaming example example posted here  for AD9361: ad9361: xilinx: Add ADC_DMA_IRQ_EXAMPLE · analogdevicesinc/no-OS@d5a9519 · GitHub

 

We are also successfully able to obtain/stream  approximately 30 Mega sample speed  when we use these two buffers. However if we add any processing of samples even for example  very simple

 

for(indexx = 0; indexx < (4096*2); indexx += 2)
            {
            data = Xil_In32((ADC_PONG_BASEADDR + (indexx * 4)));//PONG is name of one buffer
            sample_q1[indexx / 2] = (data & 0xFFFF);
            sample_i1[indexx / 2] = (data >> 16) & 0xFFFF;

            }

 

the speed is significantly reduced. It seems that processor cannot keep up with the incoming data. This is surprising for us as processor speed is set to 666 Mega Hz. Can you please point to us why this significant reduction in speed is occurring even with simple processing?

 

Your colleague is guessing that may be due to "It might be a limitation of a data bus". Can you please explain more in details.

Many thanks

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