When the ADDI7004 is used in double data port mode, I understand that the 8 differential outputs are used to transmit the data from the 4 channels. However I am a bit confused on the way to use the TCLK1 differential output clock in that mode.
Is TCLK1 always identical to TCLK0? Are all the data bits synchronized to TCLK0 or only half of them? Can I disregard TCLK1 if all the data bits from the 4 channels go to the same LVDS receiver interface that would use only one clock? Can I use only TCLK0 or only TCLK1 to receive all the data bits on my LVDS interface?